The present invention relates to a method of synthesizing logics for pipeline processors, and specifically to a method of synthesizing control logics for the registers.
A variety of means have been proposed to automatically design the logics with the increase in the scale of logics of very large computers and logic VLSIs. Methods of automatically synthesizing logics of Boolean level from the description of logic specifications at the initial stage of design can be found in Japanese Patent Laid-Open Nos. 167060/1985 and 204078/1985. In recent years, design of a pipeline control system has been widely used for improving the performance of computers, and it becomes more important to automatically design the logics for the pipeline computers.
Methods of synthesizing control logic circuits of the pipeline processor from the description of logic specifications in the initial stage of design are disclosed in Japanese Patent Laid-Open Nos. 128374/1986, 231670/1986 and 24362/1988. These methods generate logics for controlling the transfer of data so that the data is not lost due to resource conflict by analyzing the data path structure and by detecting the registers that may cause resource conflict. Resource conflict is a phenomenon in which the data transferred in parallel collide with one another at a point where the wait factor of the data transfer generates or at a point where the data meet together in a group of registers connected in plural stages. The condition in which the data are transferred in the block diagram of FIG. 2 is shown in a time chart of FIG. 4, to illustrate resource conflict.
Condition 430 denotes the condition in which the data D1 in the register B is waiting for transfer to the memory, and 420 denotes the condition in which the succeeding data D2 is transferred to the register A while the data D1 is moved to register B under the waiting condition. In this case, if it is attempted to transfer the data D2 from the register A to the register B in the third cycle, a resource conflict 440 generates in the register B.
Reference numeral 450 denotes a case where data D4 exists in the memory, and 460 denotes a case where data D3 exists in the register C in parallel with 450. A resource conflict 470 generates if it is attempted to write these data simultaneously onto the register D to which the data are to be transferred.
When the resource conflict generates, it becomes necessary to prevent the data from being lost by the collision of data. In order to prevent the resource conflict 440, for example with respect to data D1 moved from register A (510) to register B in FIG. 5, it becomes necessary to hold (520) the data D2 in the register A for two cycles until processing (530) of data D1 is finished in the register B at which time data D2 may be transferred to register B in cycle 4.
According to the prior art, a preceding register of a stage that precedes conflict register in which the data may meet together or in which the wait factor of the data transfers may develop is determined as the register that may generate resource conflict based upon the data path. In the data pathshown in FIG. 2, a register B 230 in the preceding stage of the memory M 240 is the one that may generate resource conflict with the register C 250 in the preceding stage of the selector 260. Furthermore, the resource conflict caused in the register B 230 may affect the register C 250. The selector 260 is connected through register D 270 to the circuit output pin OUT 280. Register C receives data from input IN1 210. A control logic is automatically generated to control the data holding for those registers that may develop resource conflict.